1. Field of the Invention
The present invention generally relates to synchronization circuits, and more particularly to a synchronization circuit in which a frame synchronization is established using a pointer.
2. Description of the Related Art
A synchronization multiplexing system is widely employed in the field of digital transmission systems. For example, the CCITT recommends the frame format shown in FIG. 1 in an optical digital transmission system (see the CCITT Recommendations G. 707, 708 and 709). The frame format shown in FIG. 1 is used to multiplex pieces of 50 Mbps digital data so as to transmit multiplexed data at a bit rate of a few Gbps. One frame consists of nine rows and has an overhead 1 and a payload 2. Each of the nine rows has 9N-byte overhead data, and 261N-byte payload data, wherein N is an arbitrary integer. Supervisory control information is contained in the overhead 1, and information to be actually transmitted, that is, a virtual container (VC) 3 is contained in the payload 2.
The beginning position of the virtual container is indicated by pointers H1 and H2 included in the overhead 1. The frame, format shown in FIG. 1 is the format of a frame transmitted at a bit rate equal to N times 155.52 Mbps, and is called an STM(Synchronous Transport Module)-N. According to the aforementioned CCITT Recommendations, a plurality of virtual containers 3 are included in the payload 2 of the STM-N frame format, and a plurality of pairs of pointers, such as pointers H1 and H2, are included in the overhead 1 of the STM-N frame format. Alternatively, according to the CCITT Recommendations, one virtual container 3 may be included in the payload 2 of the STM-N frame format, and a pair of pointers may be included in the overhead 1. The latter frame format is called concatenation, and the present invention is concerned with the concatenation frame format.
FIG. 2 is a block diagram of a synchronization circuit in a digital transmission system. The synchronization circuit shown in FIG. 2 comprises a frame synchronization unit 101, a frame counter 102, a decoder 103, a pointer latch 104, a payload counter 105, a comparator 106, a VC counter 107, and a zero detector 108. A clock signal shown in (A) of FIG. 3 is applied to the frame synchronizing unit 101, the frame counter 102, the pointer latch 104, the payload counter 105 and the VC counter 107.
As shown in (B) of FIG. 3, data transmitted in the frame format shown in FIG. 1 is applied to the frame synchronizing unit 101, which detects a framing pattern contained in the overhead 1. In (B) of FIG. 3, "OH" indicates the overhead 1. In response to the detection of the framing pattern, the frame counter 102 starts to count the number of bytes in the STM-N frame. The decoder 103 decodes the counter value of the frame counter 102, and generates a data enable signal shown in (C) of FIG. 3. The data enable signal causes the payload counter 105 to operate only while the payload 2 is being received. Further, the decoder 103 generates a latch timing pulse when the decoder 103 decodes the counter value indicated by the pointers H1 and H2. The latch timing pulse generated by the decoder 103 is applied to the pointer latch 104.
The pointer latch 104 latches the pointers H1 and H2 contained in the overhead 1 with the latch timing pulse, and outputs them to the comparator 106. The comparator 106 outputs a reset pulse to the VC counter 107 when the counter value of the payload counter 105 coincides with the pointer value latched in the pointer latch 104. In response to receipt of the reset pulse, the zero detector 108 detects a counter value of zero in the VC counter 107, and generates a frame pulse. As shown in (D) of FIG. 3, the frame pulse indicates the beginning position of the virtual container VC of the input data. The VC counter 107 counts the number of bytes included in the virtual container VC, and is reset every one-frame period.
It is required that the synchronization circuit operates at higher speeds as the frame bit rate increases. For example, a high-speed LSI circuit is required to handle a high-bit-rate signal having a bit rate of 622.08 Mbps (STM-4) or 2.48832 Gbps (STM-16). As is well known, compound semiconductor devices, such as GaAs devices, are capable of operating at speeds higher than CMOS devices. However, the compound semiconductor devices need more energy than the CMOS devices. In a case where the synchronous circuit shown in FIG. 2 is constructed using compound semiconductor devices, it consumes a large amount of energy.